A liquid crystal display device of the active matrix driving system is well known as one type of a conventional liquid crystal display device. As shown in FIG. 19, the liquid crystal display device of this type is provided with a pixel array 1, a scanning signal line driving circuit (referred to as gate driver hereinafter) 2, and a data signal line driving circuit (referred to as source driver hereinafter) 3. The pixel array 1 includes a number of scanning signal lines GL and a number of data signal lines SL intersecting each other, and pixels (PIX in FIG. 19) 4 arranged in a matrix.
As shown in FIG. 20, the pixel 4 is provided with a pixel transistor SW as a switching element and pixel capacitor C.sub.p including liquid crystal capacitor C.sub.L (storage capacitor C.sub.S is supplied as required). In the pixel 4 having the above arrangement, in the case where a voltage is applied to the liquid crystal capacitor C.sub.L, the transmissivity or the reflectance of the liquid crystal is modulated, and an image is displayed on the pixel array 1 in accordance with an image signal DAT.
The source driver 3 makes sampling of an inputted image signal DAT, and outputs gradation display-use data corresponding to the image signal DAT thus sampled to each data signal line SL. The gate driver 2 sequentially selects the scanning signal lines GL, and controls the opening and closing of the pixel transistor SW provided in the pixel 4. With this arrangement, the image signal (data) outputted to each data signal line SL is written into each pixel 4 and kept therein.
Incidentally, a conventional liquid crystal display device of the active matrix type preferably adopts an amorphous silicon thin film as a material for the pixel transistor SW. The amorphous silicon thin film is provided on a transparent substrate made of, for example, glass. Additionally, each of the gate driver 2 and the source driver 3 is realized by integrated circuits (IC) that are externally attached.
In contrast, in recent years, in response to a demand for improving a driving power of the pixel transistor SW due to a trend for a larger screen, for lowering the cost of mounting a driving IC, and for improving the reliability of the device upon mounting the driving IC, technology has been developed and reported for monolithically forming the pixel array 1 and the drivers 2 and 3 with a polycrystal silicon thin film. Further, in order to realize an image display device having a larger screen at a lower cost, an attempt has been made to form an active element with the polycrystal silicon thin film on a glass substrate at a processing temperature of not more than a distortion point of glass (substantially 600.degree. C.).
For example, the liquid crystal display device of FIG. 21 adopts an arrangement wherein a pixel array 1, a gate driver 2, and a source driver 3 are provided on the glass substrate 5, and a timing signal generating circuit 6 and a power source voltage generating circuit 7 are connected to the pixel array 1, the gate driver 2, and the source driver 3.
Here, an arrangement of the source driver 3 will be described. The source driver 3 can be classified into an analog type and a digital type depending on the kind of an inputted signal. In a polycrystal silicon TFT panel in which the drivers and the pixels are integrated, the analog type, especially a driver of the point sequential driving system is widely used because of its simple circuit arrangement. On the other hand, in a portable information terminal, which has been spreading rapidly in recent years, in the light of the arrangement of the system and the power consumption, it is preferable that the source driver 3 is of the digital type since the image signal is a digital signal.
The following will explain a source driver of the point sequential driving system as one example of the analog driver, and a source driver of the multi-plexer system as one example of the digital driver.
As shown in FIG. 27, in the analog type source driver of the point sequential driving system, sampling switches 13 open and close in synchronism with a pulse signal outputted from a scanning circuit 11 constituting each stage of a shift register. As a result, an analog image signal DAT (signal corresponding to three primary colors R, G, B) is outputted to the data signal line SL (SL(R), SL(G), SL(B)). Here, a buffer circuit 12 receives the pulse signal from the scanning circuit 11, and holds and amplifies the pulse signal. The buffer circuit 12 also generates a reverse signal of the pulse signal thus held and amplified as required.
As described, in the source driver of the point sequential driving system, it is required to output the analog image signal DAT to the data signal line SL within a period of time corresponding to a width of the pulse signal (tens of n sec to hundreds of n sec), thereby requiring a transistor having an excellent property (large driving power) as a sampling switch 13. Further, since the analog signal is in use, it is required to suppress the non-uniform property of each transistor.
On the other hand, the digital type source driver of the multi-plexer system operates in the following manner. As shown in FIG. 24, an inputted digital image signal DIG of 9 bits (signal corresponding to three primary colors R, G, B, 3 bits for each color) is sampled bit by bit in a latch 14 in synchronism with the pulse signal from the scanning circuit 11.
Transfer circuit 15 transfers each signal of 1 bit thus sampled at a time to a decoder 16 during a horizontal blanking period, and the transferred signals are decoded by the decoder 16. As a result, 8 decode signals per RGB are outputted from the decoder 16, and are supplied respectively to 8 analog switches 17. Then, one of 8 gradation voltages VGS is selected per RGB in accordance with the decode signals by the analog switches 17, and is outputted to the data signal lines SL (R), SL(G), and SL(B).
Incidentally, in the driving system as described above, an analog circuit such as an amplifier, which consumes a large amount of power is not employed in the driving circuit. For this reason, among the total power consumption associated with externally inputted signals such as clock signals becomes relatively greater. This is because among circuits following the shift registers, only the circuits of one stage are operated (circuits of several stages in the case of operating several stages at a time in parallel), whereas externally inputted signals are sent to the circuits of all stages simultaneously, thereby extremely increasing the capacitive load on the external input signal-use input lines.
Particularly, in the image display device of a driver-pixel integrated type, a polycrystal silicon thin film transistor is widely adopted as an active element. The polycrystal silicon thin film transistor has a larger active element size and higher driving voltage than that of monocrystal silicon transistor, thereby further increasing the power consumption associated with the externally inputted signals.
Therefore, in the image display device adopting the above-described driving system, the reduction of the loads of the externally inputted signals is effective in reducing the power consumption. The technology for reducing the power consumption in this manner is disclosed in Japanese Examined Patent Publication No. 50717/1988 (Tokukousho 63-50717) which discloses that a plurality of flip-flops constituting the shift register are divided into a plurality of groups in order to selectively supply a clock signal to each group per certain time intervals in the analog type data signal line driving circuit (data sample circuit) of the point sequential system. According to this method, the power consumption of the shift registers can be remarkably reduced.
On the other hand, in the digital type data signal line driving circuit of the multi-plexer system, the above-described method can also be adopted so as to reduce the power consumption associated with the clock signals. However, because the multi-plexer system requires a large number of image signal lines, the power consumption associated with the image signal lines increases to a level that can not be ignored.
For example, in the case of displaying an image in 512 colors, the number of the digital image signals are 9 (3 bits for each RGB), thereby requiring 9 image signal lines for inputting the digital image signals. In an arrangement wherein a number of image signal lines are provided as above, it is likely that the power consumption associated with the image signal lines, although it depends on a display pattern, exceeds the power consumption associated with the clock signal lines. Further, an image display device which displays an image in a larger number of colors, obviously, becomes affected more noticeably.